1. Field of the Invention
The present invention relates to a semiconductor storage device and a manufacturing method thereof which are applied to, e.g., a NAND flash EEPROM constituted of a partial SOI memory cell array.
2. Description of the Related Art
In a semiconductor storage device, e.g., a NAND flash memory, a problem is miniaturization of a memory cell because of a demand for an increase in capacity and a reduction in bit unit price.
However, miniaturization of a device isolation region involved by miniaturization of a memory cell causes a reduction in breakdown voltage between cells. Therefore, in order to realize miniaturization of a cell without reducing the breakdown voltage, a technology of forming a memory cell array on a silicon-on-insulator (SOI) substrate is effective. For example, JP-A 2007-110029 (KOKAI) discloses a semiconductor storage device and a manufacturing method thereof that form a NAND cell unit on a partial SOI substrate.
Here, besides miniaturization of the memory cell, further miniaturization of a selecting transistor is another problem. However, in miniaturization of the selecting transistor, especially in shrinkage in a gate length direction, it is impossible to avoid degradation in transistor characteristics such as 1) degradation in cutoff characteristics and 2) an increase in fluctuation amount of a threshold voltage (Vth) caused due to a variation of a channel length dimension by a short channel effect. Therefore, degradation in performance, e.g., a decrease in operating speed of the selecting transistor is provoked.
Therefore, in order to miniaturize the NAND flash memory, it is necessary to shrink the selecting transistor in a gate length direction while maintaining and improving characteristics of not only each memory cell but also the selecting transistor.
Therefore, realization of a semiconductor storage device and a manufacturing method thereof that can improve characteristics of the selecting transistor when a memory cell unit and the selecting transistor are formed on a semiconductor layer configured on an SOI has been demanded.